Hardware capacity overhead, in turn, negatively affects emulation performance. This causes an overflow of the hardware, which requires more hardware or makes the hardware more expensive to accommodate this increase. The counters must be synthesized in hardware, and the number of counters in a straightforward implementation can be too many for a real-life coverage specification. Hardware emulation has memory limitations that make it difficult to implement many counters. When the condition specified by the bin is met, a counter associated with the bin is incremented.
If formal verification shows that the design cannot show an event (e.g., a signal having a particular value), there is no point in testing the design in a hardware emulation or simulation environment for that event.įor functional coverage, the designer may specify many conditions for various signals and combinations of signals, and each of these conditions may be defined by a bin. In formal verification, a design is tested for attainability of the specified coverage events (i.e., whether specific conditions or transitions are coverable).
Description of Related Artĭuring functional coverage collection in hardware emulation for a signal (i.e., a net or a variable) or integral expressions of signals in a circuit design, a designer may want to understand how many times the signal or expression assumed a particular value, how many times the signal or expression had a value falling within some particular range or ranges, or how many times specific transitions occurred. This disclosure relates to functional coverage collection in hardware emulation and formal verification. The subject matter of all of the foregoing is incorporated herein by reference in their entirety. 201741028556, “Unified Functional Coverage and SVA Synthesis Flow for Emulation and Formal Verification,” filed Aug. This application claims priority to Indian Provisional Patent Application Serial No. CROSS-REFERENCE TO RELATED APPLICATION(S)
0 kommentar(er)
